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? make sure the next card you purchase has... data device corporation 105 wilbur place bohemia, new york 11716 631-567-5600 fax: 631-567-7358 www.ddc-web.com for more information contact: technical support: 1-800-ddc-5757 ext. 7771 features ? complete integrated 1553b notice 2 interface terminal direct replacement for bus-61559 aim-hy?er series functional superset of bus-61553 alm-hy series internal address and data buffers for direct interface to processor bus rt subaddress circular buffers to support bulk data transfers optional separation of rt broadcast data internal interrupt status and time tag registers internal command illegalization mil-prf-38534 processing available transmitter inhibit control for individual bus channels description ddc?s bu-61559 series of advanced integrated mux hybrids with enhanced rt features (aim-hy?er) comprise a complete interface between a microprocessor and a mil-std-1553b notice 2 bus, implementing bus controller (bc), remote terminal (rt), and monitor terminal (mt) modes. packaged in a single 78-pin dip or flat package, the bu-61559 series contains dual low-power transceivers and encoder/decoders, complete bc/rt/mt protocol logic, memory management and interrupt logic, 8k x 16 of shared static ram, and a direct, buffered interface to a host processor bus. the bu-61559 includes a number of advanced features that support mil-std-1553b notice 2 and stanag 3838. other salient features of the bu-61559 serve to provide the benefits of reduced board space requirements, enhanced software flexibility, and reduced host proces- sor overhead. the bu-61559 contains internal address latches and bidirectional data buffers to provide a direct interface to a host processor bus. alternatively, the buffers may be operated in a fully transparent mode in order to interface to up to 64k words of external shared ram and/or connect directly to a component set supporting the 20 mhz stanag 3910 bus. the memory management scheme for rt mode provides an option for separation of broadcast data, in compliance with 1553b notice 2. a circular buffer option for rt message data blocks offloads the host processor for bulk data transfer applications. the bu-61559 series hybrids operate over the full military tempera- ture range of -55 to +125c and mil-prf-38534 processing is avail- able. the hybrids are ideal for demanding military and industrial microprocessor-to-1553 applications. ? 2002 data device corporation bu-61559 series mil-std-1553b notice 2 aim-hy?er
2 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 figure 1. bu-61559 block diagram 8 (illegalization enable) illena bus-25679 7 5 4 1 2 3 low-power transceiver a tx_inh_a 8 bus-25679 7 5 4 1 2 3 low-power transceiver a tx_inh_a (rt address) rtad 4- ? , rtadp (broadcast enable) bro_ena rtfail (rtfail, rtflag) rtflag (broadcast, message timing, data strobe and error indicators) bcstrcv, cmd_str, txdta_str rxdta_str, msg_err, incmd illegallization logic dual encoder/ decoder bc/rt/mt protocol 8k x 16 dual port ram memory data memory address memory management, shared ram/ processor interface, interrupt logic tagclk ssflag memena-in memen-out,memwr, memoe int ioen, readyd transparent/buffered, mstclr, strbd, select, mem/reg, rd/wr (time tag clock) (subsystem flag) (memory control) (interrupt request) (processor control) address latches/ buffers* addr_lat a15-a ? d15-d ? data buffers* clk in (16mhz) (processor data) (processor address) (address latch control)
3 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 table 1. bu-61559 specifications parameter units value absolute maximum ratings supply voltage logic +5v transceiver +5v -15v (bu-61559x1) -12v (bu-61559x2) receiver differential voltage logic voltage input range -0.5 to 7.0 -0.5 to 7.0 +0.3 to -18.0 +0.3 to -18.0 40 max -0.5 to 7.0 v v v v vp-p v table 1. bu-61559 specifications (cont) parameter units value logic (cont) voh (vcc=4.5v, vih=2.7v, vil=0.4v) (ioh=-6.8 ma) d15 through d0, a15 through a0 (ioh=-3.4 ma) memoe , memena-out , memwr , int , ioen , read yd (ioh=-0.4 ma) r tf ail , incmd , bcstrcv , msg_err , cmd_str , txdt a_str , rxdt a_str vol (vcc=4.5v, vih=2.7v, vil=0.4v) (iol=-6.8 ma) d15 through d0, a15 through a0 (iol=2.0 ma) r tf ail , incmd , bcstrcv , msg_err , cmd_str (iol=3.4 ma) memoe , memena-out , memwr , int , ioen , read yd (iol=4.0 ma) txdt a_str , rxdt a_str ci (f=1 mhz) co (f=1 mhz) cio (f=1 mhz) d15 through d0, a15 through a0 3.7 min 3.7 min 2.4 min 0.4 max 0.4 max 0.4 max 0.4 max 50 max 10 max 50 max v v v v v v v pf pf pf power supply requirements voltages/tolerances +5v (logic) +5v (ch a, ch b) -15v (bu-61559x1) -12v (bu-61559x2) current drain +5v -15v (bu-61559x1) idle 25% duty cycle 50% duty cycle 100% duty cycle -12v (bu-61559x2) idle 25% duty cycle 50% duty cycle 100% duty cycle (see note 7) 4.5 min, 5.5 max 4.5 min, 5.5 max -15.75 min, -14.25 max -12.6 min, -11.4 max 85 typ, 170 max 5 min, 40 typ, 80 max 25 min, 80 typ, 130 max 45 min, 120 typ, 180 max 85 min, 200 typ, 280 max 5 min, 40 typ, 80 max 25 min, 90 typ, 135 max 45 min, 135 typ, 185 max 85 min, 230 typ, 305 max v v v v ma ma ma ma ma ma ma ma ma power dissipation total hybrid bu-61559x1 idle 25% duty cycle 50% duty cycle 100% duty cycle bu-61559x2 idle 25% duty cycle 50% duty cycle 100% duty cycle (see note 7) 1.025 typ, 2.050 max 1.325 typ, 2.500 max 1.625 typ, 2.950 max 2.225 typ, 3.850 max 0.905 typ, 1.810 max 1.025 typ, 2.170 max 1.445 typ, 2.470 max 1.985 typ, 3.310 max w w w w w w w w receiver differential input voltage differential input resistance (see notes 1-6) differential input capacitance (see notes 1-6) threshold voltage, transformer cou- pled, measured on stub cmrr (bu-61559x1, through bus-25679 transformer at 1mhz) (bu-61559x2, through bus-29854 transformer at 1mhz) 40 max 11 min 10 max 0.70 min, 0.86 max 50 min 50 min vp-p k ohms pf vp-p db db transmitter differential output voltage direct coupled across 35 ohms, measured on bus transformer coupled, measured on stub (for 20 vp-p min. stub voltage, consult factory) for -601 reliability grade (note 7) output noise, differential (direct cou- pled) output offset voltage, direct coupled across 35 ohms rise/fall time 6 min., 9 max 18 min, 20 typ, 27 max 20 min, 21 typ, 27 max 10 max. 90 max 100 min, 150 typ, 300 max vp-p vp-p vp-p mvp-p, diff v ns logic vih vil iih (vcc = 5.5v, vih = 2.7v) d15 through d0, a15 through a0, mem/reg , strbd , rd/wr , mstclr , select , tx_inh_a, tx_inh_b, ssfla g , transparent/b uffered , addr_lat, tagclk rtad4 through rtad0, rtadp bro_ena, r tfla g , illena memena-in , clk_in iil (vcc = 5.5v, vil = 0.4v) d15 through d0, a15 through a0, mem/reg , strbd , rd/wr , mstclr , select , tx_inh_a, tx_inh_b, ssfla g , transparent/b uffered , addr_lat, tagclk rtad4 through rtad0, rtadp bro_ena, r tfla g , illena memena-in , clk_in 2.0 min 0.8 max -346 min, -42 max -397 min, -50 max v v a a
4 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 table 1. bu-61559 specifications (cont) parameter units value power dissipation (cont) hottest die bu-61559x1 idle 25% duty cycle 50% duty cycle 100% duty cycle bu-61559x2 idle 25% duty cycle 50% duty cycle 100% duty cycle 0.45 typ, 0.68 max 0.65 typ, 1.06 max 0.875 typ, 1.45 max 1.30 typ, 2.23 max 0.39 typ, 0.59 max 0.60 typ, 0.98 max 0.81 typ, 1.36 max 1.30 typ, 2.16 max w w w w w w w w clock input frequency nominal value long term tolerance short term tolerance, 1 second duty cycle 16.0 0.1 0.01 33 min, 67 max mhz % % % physical characteristics size 78-pin ceramic qip 78-pin ceramic flat pack weight 1.80 x 2.10 x 0.21 (45.7 x 53.3 x 5.3) 1.80 x 2.10 x 0.21 (45.7 x 53.3 x 5.3) 1.7 (48.2) in. (mm.) in. (mm.) oz. (g) 1553 message timing completion of cpu write (bc start)- to start of first bc message bc intermessage gap bc response timeout rt response time rt-to rt timeout (mid-parity of transmit command to mid-sync of transmitting rt status) transmitter watchdog timeout 5.85 min, 7.21 max 13.98 min, 17.82max. 17.5 min, 19.0 typ, 22.5 max 9.8 min, 10.9 typ, 11.7 max 18.0 min, 18.75 typ, 19.5 max 768 typ s s s s s s thermal thermal resistance, junction-to-case, hottest die ( jc ) thermal resistance, case-to-ambient, hottest die ( ca ) operating junction temperature operating case temperature -b, -m -(blank) storage temperature lead temperature (soldering, 10 seconds) 6.13 10.5 -55 to +160 -55 to +125 0 to +70 -65 to +150 +300 c/w c/w c c c c c notes: the following notes are applicable to the receiver differential resistance and differential capacitance specifications: (1) specifications include both transmitter and receiver (tied together internally). (2) impedance parameters are specified directly between pins tx/rx a(b) and tx/rx a(b) of the bu-61559 hybrid. (3) it is assumed that all power and g round inputs to the hybrid are connected and that the hybrid case is connected to ground for the impedance measurement. (4) the specifications are applicable for both unpowered and powered conditions. (5) the specifications assume a 2 vrms balanced, differential, sinusoidal input. the applicable frequency range is 75 khz to 1 mhz. (6) minimum resistance and maximum capacitance parameters are guaranteed over the operating range, but are not tested. (7) -601 power supply requirements and power dissipation values will be higher. functional overview general (reference block diagram figure 1) the bu-61559 advanced integrated multiplex hybrid with enhanced rt features (aim-hy'er) comprises a complete interface between a host microprocessor bus and a dual redundant mil- std-1553b notice 2 bus. the hybrids are comprised of dual low- power transceivers and encoder/decoders, full bc/rt/mt protocol, memory management logic, 8k words of internal shared ram, and a direct, internally buffered processor interface. the bu-61559 is packaged in a four square inch hybrid package and is available in both plug-in and surface mountable (flatpack) packages. transceivers the transceiver front end of the bu-61559 aim-hy'er hybrids is implemented by means of low-power bipolar analog monolithic and thick-film hybrid technology. the transceiver requires +5 v and -15v or -12v only (no +15 v or +12v is required) and include voltage source transmitters. the voltage source transmitters pro- vide superior line driving capability for long cables and heavy amounts of bus loading. in addition, the monolithic transceivers may be modified to provide a minimum stub voltage of 20vp-p, as required for mil-std-1760 applications. consult the factory for additional information. the receiver sections of the bu-61559 are fully compliant with mil-std-1553b in terms of front end overvoltage protection, threshold, common mode rejection, and word error rate. in addi- tion, the receiver filters have been designed for optimal operation with the bu-61559's 16 mhz manchester ii decoders. mil-std-1553 protocol the 1553 protocol section of the bu-61559 includes dual encoder/decoders and complete registers, word count, timing, and sequencing logic for bus controller (bc), remote terminal (rt), and monitor terminal (mt) modes. the dual manchester ii decoders utilize a 16 mhz sampling clock, providing superior performance in terms of word error rate and tolerance to zero- crossing distortion. the encoder section of the protocol logic includes a transmitter watchdog timer. the watchdog timer mon- itors the digital encoder outputs and serves to inhibit the trans- mitters after a period of 768 s. the bc protocol supports all mil-std-1553b formats, complete error detection, and multi-message frames of up to 64 unique messages. protocol for rt mode supports all message formats and dual redundant 1553b mode codes. the bu-61559 has passed the rt validation test plan at seafac; this test encompasses the dual transceiver and all of the rt protocol logic. the monitor (mt) protocol of the bu-61559 monitors both 1553 buses. for each word received from either bus, both the 16 bits of word data plus a 16-bit identification word (?tag? word) are stored in the aim-hy'er memory space.
5 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 advanced features while maintaining functional and software compatibility to the previous generation bus-61553 series aim-hy hybrids, the bu- 61559 incorporates a number of advanced features to support 1553b notice 2. other enhancements provided by the bu-61559 serve to provide the benefits of reduced board space require- ments, expanded software flexibility, and reduced host processor overhead. internal tri-state buffers the bu-61559 contains internal address latches and bidirection- al data buffers to provide a direct interface to either a multiplexed or a non-multiplexed processor bus. alternatively, the latches and buffers may be operated in a fully transparent mode to interface to up to 64k words of external shared ram and/or a component set supporting the stanag 3910 20 mhz data bus. memory management the bu-61559 incorporates complete memory management and processor interface logic. the software interface to the host processor is implemented by means of eight internal registers plus a 64k word shared ram address space, which generally includes the 8k words of internal ram. for all three modes, a stack area of ram is maintained. in bc mode, the stack allows for the schedul- ing of multi-message frames. for all three modes, the stack pro- vides a real time chronology of all messages processed. in addi- tion to the stack processing, the memory management logic per- forms storage, retrieval, and manipulation functions involving pointer and message data structures for all three modes. the bu-61559 provides a number of programmable options for rt mode memory management. in compliance with mil-std- 1553b notice 2, received data from broadcast messages may be optionally separated from non-broadcast received data. for each transmit, receive or broadcast subaddress, either a single-mes- sage data block or a variable-sized (128 to 8192 words) circular buffer may be allocated for data storage. in addition to helping ensure data consistency, the circular buffer feature provides a means of greatly reducing host processor overhead for bulk data transfer applications. end-of-message interrupts may be enabled either globally, following error messages on a tx/rx/bcst-subad- dress basis, or when any particular tx/rx/bcst-subaddress circu- lar buffer reaches its lower boundary. in addition to interrupts for rt subaddress and circular buffer rollover conditions, the proces- sor interface logic provides maskable interrupts and a 9-bit interrupt status register for end of message, end of bc message list, erroneous messages, status set (bc mode), time tag register rollover, and rt address parity error conditions. the interrupt status register allows the host processor to determine the cause of all interrupts by means of a single read operation. internal command illegalization the bu-61559 implements internal command illegalization for rt mode. the internal illegalization eliminates the need for an external prom, pld, or ram device. the illegalization architec- ture allows for any subset of the 4096 possible combinations of broadcast/own address, t/r bit, subaddress, and word count/mode code to be illegalized. the bu-61559 illegalization scheme is under software control of the host processor. as a result, it is inherently self-testable. internal time tag the bu-61559 includes an internal read/write time tag register. this register is a cpu read/write 16-bit counter with a program- mable resolution of either 2, 4, 8, 16, 32, or 64 s per lsb. the time tag register may also be clocked from an external oscilla- tor. another option allows the time tag register to be incre- mented under software control. this supports self-test for the time tag register. for each message processed, the value of the time tag register is loaded into the second location of the respective descriptor stack entry (?time tag word?) for both bc and rt modes. additional options are provided to clear the time tag register following a synchronize (without data) mode command or load the time tag register following a synchronize (with data) mode command. another option enables an interrupt request and a bit in the interrupt status register to be set when the time tag register rolls over from 0000 to ffff. assuming the time tag register is not loaded or reset, this will occur at approximately 4- second time intervals for 64 s/lsb resolution, down to 131 ms intervals for 2 s/lsb resolution. another programmable option for rt mode is for the service request status word bit to be automatically cleared following the bu-61559's response to a transmit vector word mode command. interface to stanag 3910 20 mhz fiber optic bus for applications requiring a higher rate of data transfer than mil- std-1553's 1 mbps, it is possible to interface the bu-61559 directly to a component set supporting stanag 3910. a stanag 3910 bus operates as an adjunct to, and is controlled by, a mil-std-1553b notice 2 (stanag 3838) bus. the stanag 3910 standard defines a manchester ii encoded serial data bus with a data rate of 20 mbps, allowing for both electrical and fiber optic implementations. stanag 3910 is intended for high-speed bulk data transfers, supporting message lengths of up to 4096 words. clock input the bu-61559 requires an external 16 mhz clock input. all inter- nal timing is derived from this clock. refer to figure 1 for the short-term and long-term accuracy requirements of the input clock frequency.
6 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 internal registers, memory management, and interrupts the software interface of the bu-61559 to the host processor consists of eight internal registers plus 64k x 16 of shared mem- ory address space. the bu-61559's 8k x 16 of internal ram resides in this address space. the address mapping and accessibility for the eight registers is defined as follows: address lines a2 a0 a1 0 0 interrupt mask register (rd/wr) 0 0 1 configuration register # 1 (rd/wr) 0 0 0 configuration register # 2 (rd/wr) 1 0 1 start/reset register (wr) 1 0 1 stack pointer register (rd) 1 1 0 subaddress control word register (rd/wr) 0 1 1 time tag register (rd/wr) 0 1 0 interrupt status register (rd) 1 1 1 reserved 1 register description/accessibility the interrupt mask register is used to enable and disable inter- rupt requests for various conditions. configuration registers #1 and #2 are used to select the bu-61559's mode of operation as well as for software control of rt status word bits, active memory area, bc stop-on-error, rt memory management mode selection, and other functions involving the service request status bit, interrupts, and resolution and operation of the time tag register. the start/reset register is used for ?command? type functions, such as software reset and bc/mt start as well as interrupt reset, time tag reset, and time tag register test. the stack pointer register allows the host cpu to determine the pointer location for the current or most recent message when the bu- 61559 is in bc or rt modes. the subaddress control word register allows the host proces- sor access to the current or most recent subaddress control word; the read/write accessibility of this register can be used to facilitate the testing of the bu-61559. the 16-bit time tag register maintains the value of a real time clock. the resolution of this register is programmable from among 2, 4, 8, 16, 32, and 64 s/lsb. the time tag register may also be clocked from an external oscillator. the current value of the time tag register is written to the stack area of ram during start-of-message (som) and end-of-message (eom) sequences in bc and rt modes. the interrupt status register mirrors the interrupt mask register and contains a master interrupt bit. it allows the host processor to determine the cause of an interrupt request by means of a sin- gle read operation. the bit maps of the eight registers are defined in figures 2 and 3. block status word the block status word is stored in the first location of the message block descriptor in the stack area of the shared ram for both bc and rt modes. it is updated by the 1553 memory management logic both at the beginning and at the end of the respective message. it contains information relating to whether the message is in progress or has been completed, what chan- nel it was processed on, and whether or not there were any errors in the message. figure 2. interrupt mask register figure 3. configuration register #1
7 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 figure 5. start/reset register figure 6. stack pointer register figure 8. time tag register figure 4. configuration register #2 figure 7. subaddress control word register figure 9. interrupt status register * the bc control word/rt subaddress control word register cannot be written to when the bu-61559d1 is in rt mode, or during the time of a bc frame (follow- ing a bc start command) in bc mode. the bu-61559d1?s bc control word/rt subaddress control word register may be read at any time. *
8 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 time tag the second word of the message block descriptor is the 16-bit time tag. the time tag value is written from the time tag register during the bc som sequence. the resolution of the time tag register is programmable from among 2, 4, 8, 16, 32, 64, or ?external? (variable) s/lsb. after the host processor has determined the message status by reading the message block descriptor, it may then read the results of the message from the respective message block. that is, it should read the received loopback word, followed by the rt status word(s), and possibly data words received from the responding rt. figure 10. block status word bc operation the bc protocol of the bu-61559 implements all mil-std- 1553b message formats. message format is programmable on a message-by-message basis by means of individual bc control words and the t/r bit of the command word to be transmitted. in addition to message format, the bc control word allows bus channel, self-test, and status word masking to be specified on an individual message basis. the bc performs all error checking required by 1553b. this includes validation of sync type and encoding, manchester ii encoding, parity, bit count, word count, and status word rt address field. rt response time is verified to be less than the bu-61559's response timeout value of 17.5 to 22.5 s. bc memory organization table 2 illustrates a typical memory map for bc mode. it is important to note that the only fixed locations for the bu-61559 in bc mode are for the two stack pointers (address locations 0100 (hex) and 0104) and for the two message count locations (0101 and 0105). the user is free to locate the stack and bc message blocks anywhere else within the 64k (8k internal) shared ram address space. for simplicity of illustration, 64 words are allocated for each bc message block in the typical bc memory map of table 2. note, however, that the actual maximum size of a bc message block is 38 words, for an rt-to-rt transfer of 32 data words (control + 2 commands + loopback + 2 status words + 32 data words). therefore, it is possible to pack more messages into the shared ram address space, particularly if the 256-word boundaries are disabled. active areas double buffering the active area facility provides a global mechanism for dividing the shared ram into ?active? and ?non-active? areas. at any point in time, only the various data structures within the ?active? area are accessed by the internal 1553 memory management logic. it should be noted, however, that at any point in time, both the active and non-active areas are accessible by the host proces- sor. an overview of the bu-61559's memory management scheme for bc mode is illustrated in figure 11. the bc may be pro- grammed to transmit multi-message frames of up to 64 unique messages and up to 256 total messages per frame. the number of messages to be processed is programmable by means of a fixed message count location in the shared ram. in addition, the host processor must initialize a second fixed location as the stack pointer. this ram location contains a pointer that references the four-word message block descriptor (in the stack area of shared ram) for each message to be processed. each message resides in a designated message block area of the shared ram. the starting location for each message block is specified by a pointer that is stored in the fourth location of the block descriptor for the respective message. this pointer must be loaded by the host processor before the message is processed. the first word of each bc message block is the bc control word. address (hex) 0000-00ff stack a 0100 stack pointer a (fixed location) 0101 message count a (fixed location) 0104 stack pointer b (fixed location) 0105 message count b (fixed location) 0140-017f message block 0 0180-01bf message block 1 01c0-01ff message block 2 1ec0-1eff message block 118 1f00-1fff stack b table 2. typical bc memory map (shown for 8k ram) description note: bits 7 through 0 will read as ff (hex) after the block status word has been written to shared ram during a start-of-message (som) or end-of- message (eom) sequence.
9 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 bc control word for each of the bc message block formats, the first word in the block is the bc control word. the bc control word is not trans- mitted on the 1553 bus. instead, it contains bits that select the active bus and message format, enable off-line self-test, and specifies the ?expected value? of the broadcast command received rt status bit. the bc control word is followed by the command word to be transmitted, and subsequently by a second command word (for an rt-to-rt transfer), followed by data words to be transmitted (for receive commands). the location after the last word to be transmitted is reserved for the loopback word. the loopback word is an on-line self-test feature in which the received version of the last transmitted word is stored in the next location in the shared ram. the subsequent locations after the loopback word are reserved for received status words and data words (for transmit messages). the next word in ram after the bc control word is the mil-std- 1553b command word (for an rt-to-rt or rt-to-broadcast transfer, it is the first of two command words). this word is read by the 1553 protocol logic and transmitted on the 1553 bus. the (first) command word is possibly followed by a second command word or data words to be read from ram and trans- mitted. the location in ram after the last transmitted word is reserved for the loopback word. subsequent locations in the shared ram are reserved for status and possibly data words anticipated to be received from the responding rt(s). assuming that the rt responds before a bc response timeout occurs, these word(s) are stored in the allocated locations in the shared ram. if the loopback test passes, and the rt responds before the bc response timer times out with a ?correct? rt status word (correct rt address and the ?expected value? for the lower 11 bits), followed by the correct number of valid data words, the block status word will be written to indicate ?end of message, no errors? during the bc end-of-message sequence. note that for an rt-to-rt transfer, the bu-61559 bc checks the status words from both the transmitting and receiving rts. figure 12. bc control word figure 11. bc memory management
10 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 bc message block formats in bc mode, the bu-61559 supports all mil-std-1553b mes- sage formats. for each 1553b message format, the bu-61559 mandates a specific sequence of words within the bc message block. this includes locations for the control, command, and (transmitted) data words that are loaded by the host processor to be read from ram by the bc protocol logic. in addition, sub- sequent contiguous locations must be allocated for storage of received loopback, rt status, and data words. figure 13 illustrates the organization of the bc message blocks for the var- ious mil-std-1553b message formats. note that for all of the message formats, the bc control word is located in the first location of the message block. bc interrupts in bc mode, the host processor may be interrupted after every bc message (eom interrupt), after the entire message frame has been processed (bc end of frame interrupt), after erro- neous messages (format error interrupt), after a status word address mismatch or ?unexpected? status word bit values (status set interrupt) and/or after the time tag register has rolled over. the user has the further option of programming the bc for stop-on-error operation. alternatively, the host processor may determine if the current message frame has been complet- ed by polling the contents of either the interrupt status register or the stack pointer or message count ram locations. bc descriptor stack the host processor may determine the status of individual mes- sages by reading the first two locations of the respective descrip- tor block. the first location within the descriptor block contains the block status word. in bc mode, the block status word con- tains information relating to whether the message is in progress or has been completed, which bus channel it was transmitted on and whether there were any errors in the message. the second location contains the time tag word. the current value of the internal time tag register is written to the time tag word during both the bc start-of-message (som) and end-of- message (eom) transfer sequences. the third location of the bc message block descriptor is reserved (not used). the fourth location is used to store the message block address word. the message block address must be loaded by the host processor before the message is processed. it is then used as a pointer by the bu- 61559 memory management logic for accessing the start of the respective message block. the two other fixed locations in the shared ram address space that must be initialized by the host processor for bc mode are the stack pointer and message counter locations. the stack pointers are located in address locations 0100 (for area a) and 0104 (for area b). the stack pointer should be initialized to point to the first word of the message block descriptor (block status word) for the first message to be processed. the message counters are located in addresses 0101 (for area a) and 0105 (for area b). the active area message counter must be pre- loaded by the host processor with the ones complement of the number of messages to be processed (e.g., fffe represents a message count of 1). the message counter is incremented by one following each bc message processed. figure 13. bc message block formats
11 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 rt operation some of the principal features of the bu-61559 for remote terminal (rt) mode include implementation of all mil-std- 1553b formats and dual redundant mode codes, internal com- mand illegalizing, implementation of the ?busy? function, an inter- nally formulated bit word, and comprehensive error checking, including rt-to-rt transfer errors. remote terminal address for the bu-61559 is pin programma- ble. six input pins, rtad4 through rtad0 plus rtadp, need to be correctly strapped for rt address and odd address parity to enable the bu-61559 to recognize and respond to its own dis- crete rt address. in addition, the upper two bits of configuration register #1 must be programmed for 1 and 0 respectively to con- figure the bu-61559 for rt mode. ?active area? and the rt status word bits subsystem flag, service request, busy, and dynamic bus control accept are also software programmable by means of configuration register #1. the bu-61559's advanced rt features are selectable by means of configuration register #2. the two most important of these features are the enhanced rt mode (bit 1) and the option for separation of broadcast messages (bit 0). if the enhanced mode is not chosen, the bu-61559's memory man- agement scheme defaults to that of the bus-61553 aim-hy. in this configuration, each t/r-subaddress is mapped to a single data block by means of its respective lookup table entry. in this mode, the data block for each t/r-subaddress is repeatedly overwritten or overread. if the enhanced mode is selected, the user has the option of selecting either the ?single message? mode or making use of the circular buffer option, on a transmit/receive/broadcast-subaddress basis. the circular buffer option supports bulk data transfers by automatically access- ing/storing multiple receive or transmit messages per t/r-sub- address, up to a maximum of 8192 words. the bu-61559 includes an option for internal command illegaliz- ing. if this option is utilized, 256 words of the bu-61559's 8k x 16 of internal dual port ram may be dedicated for the command illegalization function. the bu-61559 allows any subset of the 4096 possible 1553 command words to be illegalized as a func- tion of broadcast/own address, t/r bit, subaddress, and word count/mode code. other rt options controlled by configuration register #2 include automatic clearing of the service request status word bit fol- lowing a transmit vector word mode command and capabilities to clear and/or load the time tag register following receipt of synchronize mode commands. rt memory organization a typical memory map for the bu-61559 in rt mode is illustrat- ed in table 3. as in bc mode, the two stack pointers reside in fixed locations in the shared ram address space: address 0100 (hex) for the area a stack pointer and address 0104 for the area b stack pointer. in addition to the stack pointer, for rt mode there are three other areas of the aim-hy'er address space that are designated as fixed locations. these are for the area a and area b lookup tables and for the optional section of the shared internal dual port ram that may be selected for the use of com- mand illegalizing. the rt lookup tables, which provide a mech- anism for mapping data blocks for individual tx/rx/bcst-subad- dresses to areas in the ram, are located in address range 0140 to 01bf for area a and address range 01c0 to 023f for area b. the rt lookup tables include subaddress control words as well as the individual data block pointers. the subaddress control address (hex) 0000-00ff stack a 0100 stack pointer a (fixed location) 0104 stack pointer b (fixed location) 0140-01bf lookup table a (fixed area) 01c0-023f lookup table b (fixed area) 0240-025f data block 0 0260-027f data block 1 1ee0-1eff data block 221 1f00-1fff stack b 02e0-02ff data block 6 0300-03ff command illegalizing 0400-041f data block 7 0420-043f data block 8 0000-00ff stack a 0100 stack pointer a (fixed location) 0104 stack pointer b (fixed location) 0140-01bf lookup table a (fixed area) 01c0-023f lookup table b (fixed area) 0240-025f data block 0 0260-027f data block 1 0280-029f data block 2 02a0-02bf data block 3 1ee0-1eff data block 229 1f00-1fff stack b table 3a. typical rt memory map (with the command illegalizing option selected) description address (hex) table 3b. typical rt memory map (with the command illegalizing option not selected) description
12 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 words are used to specify the rt memory management scheme for each tx/rx/bcst-subaddresses. if used, address range 0300- 03ff is dedicated as the illegalizing section of ram. the actual stack ram area as well as the individual data blocks may be located in any of the non-fixed areas in the shared ram address space. table 3a illustrates the rt memory map for the case where the internal illegalizing feature is used. by connecting the illena input to logic 1 (+5v), address locations 0300-03ff (hex) are dedicated for the command illegalizing function. table 3b illus- trates the typical memory map for the case when the internal ille- galization feature is not used. in this instance, illena must be strapped to logic 0 (ground) so that address locations 0300-03ff (hex) may be used for storage of stack data or message data blocks. active area double buffering the bu-61559 provides a global double buffering mechanism by means of bit 13, current area b/a , of configuration register #1. at any point in time, this allows for one stack point- er, stack area, lookup table, and set of data blocks to be desig- nated as ?active? (used for the processing of 1553 messages) and the alternate set of respective data structures to be desig- nated as ?non-active?. both the ?active? and ?non-active? ram areas are always accessible by the host processor. rt lookup tables referring to table 4, the rt lookup tables are expanded beyond those of the bus-61553. in the 61553, the lookup tables are 64 words each, containing the lookup table pointers for the 32 receive subaddresses and the 32 transmit subad- dresses. for the bu-61559, there are an additional 64 words in subaddress control word lookup table (optional) sacw sa0 sacw sa31 0220 023f 01a0 01bf broadcast lookup table (optional) bcst sa0 bcst sa31 0200 021f 0180 019f transmit lookup table tx sa0 tx sa31 01e0 01ff 0160 017f receive (/broadcast) lookup table rx(/bcst) sa0 rx(/bcst) sa31 01c0 01df 0140 015f comment description area b area a table 4. rt look-up tables each of the two lookup tables. thirty two (32) of these words provide optional separation of broadcast messages. the last 32 words are subaddress control words, one appropriated for each rt subaddress. subaddress control word referring to figure 13.1 and table 5, in the enhanced rt memory management mode, each of the 32 subaddress control words specifies the memory management and interrupt schemes for the respective subaddress. for each subaddress control word, five bits control the memory management scheme and interrupts for each of transmit, receive, and broadcast mes- sages. for each transmit, receive, or broadcast subaddress, three bits are used to specify the memory management scheme. for each tx/rx/bcst subaddress, the memory management scheme may be selected for either the ?single message? mode or the ?circular buffer? mode. in the single message mode, a single data block is repeatedly overread (for transmit data) or overwritten (for receive or broad- cast data). alternatively, in the circular buffer mode, data words for successive messages to/from any particular tx/rx/bcst sub- addresses are read from or written to the next contiguous block of locations in the respective circular buffer. the size of the circular buffer for each transmit, receive, or broadcast subaddress may be programmed for 128, 256, 512, 1024, 2048, 4096, or 8192 words. for each tx/rx/bcst subad- dress, two bits of the subaddress control word are used to enable interrupts. one of these bits will result in an interrupt fol- lowing every message directed to the specific tx/rx/bcst sub- figure 13.1 subaddress control word bit map
13 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 address. the other of these two bits will result in an interrupt at the end of a message if the message resulted in the lookup table pointer for the respective tx/rx/bcst-subaddress crossing the lower boundary of the circular buffer, rolling over to the top of the buffer. single message mode if bit 1 of configuration register #2 is logic 0, the bu-61559's memory management scheme assumes its default or non- enhanced mode. in the non-enhanced rt operation, the single message memory management mode is used for all receive, transmit, or broadcast subaddresses. in addition, under the enhanced rt memory management scheme, the single mes- sage mode may still be used for individual receive, transmit, and/or broadcast subaddresses. this is the case if the three applicable ?memory management? bits in the respective subaddress control word are set to logic 0. the operation of the single message rt memory management mode is illustrated in figure 14. in the single message mode, the lookup table must be loaded by the host processor. at the start of each message, the lookup table entry is stored in the third position of the respective message block descriptor in the stack area of ram. received data words are written to or trans- mitted data words are read from the data block referenced by the respective lookup table pointer. in the single message mode, the current lookup table pointer is not written to by the bu-61559 memory management logic at the end of a message. therefore, if a subsequent message is processed for the same subaddress, the same data block will be overwritten or over- read. circular buffer mode in the enhanced rt memory management mode, individual transmit, receive, and broadcast subaddresses may be pro- grammed for either the single message or circular buffer modes. circular buffer of specified size. 8192-word 1 1 1 4096-word 0 1 1 1024-word 0 0 1 512-word 1 1 0 256-word 0 1 0 128-word 1 0 0 single buffer 0 0 0 mm0 description comment mm1 mm2 table 5. subaddress control word - memory management options 2048-word 1 0 1 the operation of the circular buffer rt memory management mode is illustrated in figure 15. as in the non-enhanced mode, the individual lookup table entries are initially loaded by the host processor. at the start of each message, the lookup table entry is stored in the third position of the respective message block descriptor in the stack area of ram. receive or transmit data words are transferred to (from) the circular buffer, starting at the location referenced by the lookup table pointer. under any of the following conditions, the location after the last address location accessed for the message will be stored into the respective lookup table pointer location following the end of a message: (1) if bit 11 of configuration register # 2 (over- write invalid data) is logic 0, (2) following a transmit mes- sage, or (3) following a valid receive or broadcast message, if bit 11 of configuration register #2 is logic 1. in this way, data for the next message for the respective tx/rx/bcst-subaddress will be accessed to/from the next lower contiguous block of address locations in the circular buffer. if the overwrite invalid data bit (bit 11) of configuration register #2 is logic ?1?, the location after the last word accessed for the message is stored into the respective lookup table loca- tion only following a valid received (or transmitted) mes- sage . assuming that the value of the lookup table pointer is updated, data for the next message for the respective tx/rx/bcst subaddress will be accessed to/from the next lower contiguous block of locations in the circular buffer. if the over- write invalid data bit is set, the lookup table pointer will not be updated at the end of the message if there was an error in the message. this allows failed messages in a bulk data trans- fer to be retried without disturbing the circular buffer data struc- ture, and without intervention by the rt's host processor. when the pointer reaches the lower boundary of the circular buffer (located at 128-, 256-, . . . 8192-word boundaries in the shared ram address space), the pointer moves to the top boundary of the circular buffer, as shown in figure 15. it should be noted that the pointer to the start of the rt message block is stored in the third location of the message block descrip- tor (in the stack) for the single message mode as well as for the circular buffer mode. rt stack and interrupts in rt mode, the stack area of ram contains a real time chronol- ogy of all messages processed by the bu-61559. similar to bc mode, there is a four-word block descriptor in the stack for each message processed. the four entries to each block descriptor are the block status word, time tag word, the pointer to the start of the data block, and the 16-bit received command word. prior to the processing of messages, the host processor should initialize the stack pointer. in some applications, it may also prove helpful to ?zero out? the stack area prior to receiving messages.
14 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 in rt mode, the host processor may determine that a message has been processed either by means of interrupts or by polling the interrupt status register or the stack pointer. the stack pointer increments by four (modulo 256) during the start-of-message sequence for each message processed. after processing a message, the host cpu should read the block status word, time tag, data block starting address, and command word received from the message block descriptor in the stack. assuming a valid message was received, it may then read the received data from the respective data block. the bu-61559 offers a great deal of flexibility in terms of rt interrupt processing. in some systems, the transmission or reception of a message with a particular subaddress denotes the end of a complete set of consistent data. in this instance, the user should use the rt subaddress control word interrupt in order to issue an interrupt request only for a particular t/r-subaddress , rather than following every mes- sage. one technique would then be for the host processor to switch the active area of shared ram, by toggling bit 13 of configuration register #1 at this time. this allows the next group of messages comprising a consistent data set to be stored in the alternate area of the shared ram address space. implementing bulk data transfers in systems involving bulk data transfers over the 1553 bus to/from the same subaddress, the host cpu should set the overwrite invalid data bit (bit 11) of configuration register #2 and enable the rt circular buffer rollover interrupt request. by doing so, the routine transfer of multiple messages to the selected subaddress, including errors and retries , is transparent to the host processor. the bu-61559 will issue an interrupt request only after it has received the antic- ipated number of valid data words to the particular subaddress. the anticipated number of words to be received (or transmitted) is programmable up to 8192 words. rt command illegalization the bu-61559 provides an internal mechanism for rt command word illegalizing. the scheme utilizes a 256-word area in the bu-61559's internal dual port ram. a benefit of this feature is reduced printed circuit board space requirements, by eliminating the need for an external prom, pld, or ram device to perform the illegalizing function. the bu-61559's illegalization scheme provides the maximum in flexibility, allowing any subset of the 4096 possible combinations of broadcast/own address, t/r bit, subaddress, and word count/mode code to be illegalized. another advantage of the ram-based illegalization scheme is that it is inherently self-testable. in order to use the bu-61559's internal dual port ram for rt command illegalizing, it is necessary to connect the input signal illena to logic 1. by so doing, address locations 0300 through 03ff are dedicated for the message illegalizing function and must not be used for stack or data block storage. the rt com- mand illegalization option may be disabled by connecting illena to logic 0. in this instance, the bu-61559 assumes all received command words are legal. if illena is connected to logic 0, address locations 0300 through 03ff may be used for the storage of stacks or data blocks. it should be noted that the state of the illena input has no effect for bc or monitor (mt) modes. if the command illegalizing feature is used, address locations 0300-03ff must be mapped to the respective locations in the bu-61559's 8k x 16 of internal shared ram. addressing the illegalization table the addressing scheme of the illegalization ram is illustrated by figure 16. as shown, the base address of the illegalizing ram is 0300 (hex). the index into the illegalizing ram is formulated by means of br o adcast /own address, t/r bit, subaddress, and the msb of the word count/mode code field (wc/mc4). the internal ram has 256 words reserved for command illegal- ization. broadcast commands may be illegalized separately from non-broadcast receive commands and mode commands. commands may be illegalized down to the word count level. for example, a one-word receive command to subaddress 1 may be legal, while a 2-word receive command to subaddress 1 may be illegalized. the first 64 words of the illegalization table refer to broadcast receive commands (two words per subaddress). the next 64 words refer to broadcast transmit commands. since non-mode code broadcast transmit commands are by definition invalid, this section of the table (except for subaddresses 0 and 31) does not need to be initialized by the user. the next 64 words correspond to non-broadcast receive commands. the final 64 words refer to non-broadcast transmit commands. messages with word count/ mode code (wc/mc) fields between 0 and 15 may be illegalized by setting the corresponding data bits for the respective even- numbered address locations in the illegalization table. likewise, messages with wc/mc fields between 16 and 31 may be illegal- ized by setting the corresponding data bits for the respective odd-numbered address locations in the illegalization table. the following should be noted with regards to command illegal- ization: (1) to illegalize a particular word count for a given broadcast/own address-t/r subaddress, the appropriate bit position in the respective illegalization word should be set to logic 1. a bit value of logic 0 designates the respective command word as a legal command. the bu-61559 will respond to an illegal- ized non-broadcast command with the message error bit set in its rt status word.
15 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 figure 14. rt memory management - single message mode figure 15. rt memory management - circular buffer mode
16 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 (2) for subaddresses 00001 through 11110, the ?wc/mc? field specifies the word count field of the respective command word. for subaddresses 00000 and 11111, the ?wc/mc? field specifies the mode code field of the respective command word. (3) since non-mode code broadcast transmit messages are not defined by mil-std-1553b, the sixty (60) words in the illegal- ization ram, addresses 0342 through 037d, corresponding to these commands do not need to be initialized. the bu-61559 will not respond to a non-mode code broadcast transmit com- mand, but will automatically set the message error bit in its internal status register, regardless of whether or not the cor- responding bit in the illegalization ram has been set. if the next message is a transmit status or transmit last command mode code, the bu-61559 will respond with its message error bit set. broadcast option in rt mode, the bu-61559 supports the use of broadcast mes- sages as a pin-programmable option. if the input signal bro_ena is connected to logic 1 (+5v), the bu-61559 will rec- ognize rt address 31 as the broadcast address. if bro_ena is connected to logic 0 (ground), then rt address 31 will not be recognized as the broadcast address and may be used as a dis- crete terminal address. mil-std-1553b stipulates that rt address 31 shall not be assigned as a discrete terminal address. busy bit if the host cpu asserts the b usy bit low in configuration register #1, the bu-61559 will respond with the busy bit set in its rt status word. for a receive command, words will be writ- ten to the data block in the shared ram referenced by the respective lookup table location. for a transmit command, the aim will respond with status/busy, but no data words will be transmitted. dynamic bus control acceptance the dynamic bus control acceptance bit in the rt status word will only be set if the d ynamic b us a ccept bit in the configuration register is set to logic 0 and the rt is responding to a dynamic bus control mode code. it should be noted that the bu-61559 will not automatically switch from rt to bc mode fol- lowing reception (and acceptance) of a dynamic bus control mode command. subsystem flag status word bit the subsystem flag status word bit is controllable from the host processor by means of bit 8 of configuration register #1, ssfla g . the subsystem flag status bit will be set if ssfla g is programmed to logic ?0?. in addition, the subsystem flag status word bit will also be set if a logic ?0? is applied to the ssfla g input pin. for some applications, the output of a cpu watchdog timer may be connected to the ssfla g input pin. this provides a mechanism for the system bus controller to determine that the rt's host processor has failed. figure 16. illegalizing ram address definition r tf ail , r tfla g signals the bu-61559 provides a degree of flexibility for the purposes of monitoring of the rt built-in self-test by the host processor as well as in formulation of the rt flag status word bit. this is accomplished by bringing out the r tf ail output signal and the r tfla g input signal. the r tf ail output is updated following every non-broadcast message processed by the bu-61559 in rt mode. r tf ail will be asserted low following either a timeout of the transmitter failsafe timer (768 s) and/or a failure of the looptest. a looptest failure indicates either a mismatch in the bit pattern and/or an invalid word for the received version of the last transmitted word. the r tla g input is used to control the rt flag bit in the bu- 61559's rt status word. it is sampled following the reception of all valid non-broadcast command words. in most applications, r tf ail will be connected directly to r tfla g . in other instances, provisions may be implemented such that the host processor can control the r tfla g input to the bu-61559. this allows the cpu to assert r tfla g low following failure of a software-driven self- test of the bu-61559. monitor operation to initialize the bu-61559 for monitor (mt) mode, the host processor should program the upper two bits of configuration register #1 to 0 and 1 respectively. next, the stack pointer for the active area should be loaded with the starting location of the monitor stack in the bu-61559 shared ram address space. finally, to start the monitor, a ?start? command should be issued by means of the start/reset register. in monitor mode, the bu-61559 continuously monitors both 1553 bus channels, storing all words to the shared ram in the order in which they are received. for each word received from the 1553 bus, the bu-61559 stores two 16-bit words to the shared ram
17 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 address space. the first of the two words is the actual 16 bits of data from the received word. the second word is the identification (id) or ?tag? word. the monitor id word contains a word flag bit (always logic 1) plus information relating to bus channel, word validity, command-status/data sync type, and inter-word gap time infor- mation. this latter field includes a ?contiguous data? bit as well as an 8-bit gap time field, indicating 0 to 127 s with a resolution of 0.5 s per lsb. to take the bu-61559 monitor off-line, the host cpu must issue a reset command to the start/reset register. table 6 illustrates a typical memory map for monitor mode. the bu-61559 identification word is defined in figure 17. self-test the bu-61559 contains a number of self-test features. the inter- nal registers and shared ram are accessible to the host proces- sor at all times. the inclusion of wraparound capability for the 1553 front end transceiver and encoder/decoder supports bc off-line and on-line self-test as well as rt on-line self-test. the internal registers and shared ram can be tested by means of host processor software routines to implement ?checker- board?, ?walking zero?, and ?walking one? patterns and/or by writ- ing the address as the data to each ram location and then read- ing back and verifying the contents of the entire ram array. a common element of all of the wraparound self-test features is the method by which loopback words are checked. in each case, the last word transmitted by the bc or rt is looped back into the active manchester ii decoder. the received version of this word is verified for: (1) validity (sync field and manchester ii bit encod- ing, bit count, and parity), and (2) a bit-by-bit comparison to the transmitted version of the word. the loopback test is considered to have failed if either of these two criteria is not met. in the bc off-line self-test, the 1553 transmitter is inhibited, and the encoder output is muxed directly into the respective decoder input. for both the bc off-line and on-line self-tests, the received version of the last transmitted word is stored in the next location of the shared ram following the transmitted loopback word. for both the bc and rt loopback tests, the looptest fail bit in the message's block status word will be set as a result of a failed loop test. interface to mil-std-1553 bus interfacing the bu-61559 to a mil-std-1553 bus requires a pair of bus-25679 or bus-29854 pulse transformers. these trans- formers, or qpl equivalents, are available from beta transformer technology corporation, a subsidiary of ddc. the bu-61559 hybrid and beta transformers may be wired for either direct cou- pled or stub coupled configurations. the interface between a bu-61559x1 or bu-61559x2 and a mil-std-1553 bus is illustrated in figure 18. buffered processor interface as a means of reducing printed circuit board space require- ments, 16-bit address and data buffers are incorporated into the bu-61559 aim-hy'er. as determined by the strapping of the input signal transpar- ent/b uffered , the bu-61559 processor interface may be configured for either of two modes. transparent/b uffered should be strapped to logic ?0? for buffered mode, logic ?1? for transparent mode. stack pointer (fixed location) 0100 ffff 0006 0004 second identification word 0003 second received 1553 word 0002 first identification word 0001 first received 1553 word 0000 address (hex) function table 6. typical mt memory map 0005 figure 17. monitor identification word
18 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 buffered mode in the buffered mode (reference figure 19), the processor data and address buses connect directly to the corresponding buses of the bu-61559. in this mode, the shared memory size is limit- ed to the 8k x 16 of internal ram. in the buffered mode, the internal address latches and data buffers serve to isolate the external processor address/data buses from the internal memo- ry address/data buses. the bu-61559 supports a direct interface to a multiplexed processor bus by means of the input signal addr_lat. when addr_lat is high, the latch/buffers for a15-a0 are in their trans- parent mode. when addr_lat is low, the latch/buffers for a15- a0 are in their latched mode. in the buffered mode, the address latch/buffers are directed inward for cpu accesses and are dis- abled for 1553 accesses. the bidirectional data buffers are directed inward for cpu write transfers, outward for cpu read transfers, and are disabled for 1553 transfers. figure 18. bu-61559x1, bu-61559x2 interface to 1553 bus notes for figure 18: (1) shown for one of two redundant buses that interface to the bu-61559/60 series hybrid. (2) transmitted voltage level on 1553 bus is 6 vp-p min, 7 vp-p nominal, 9 vp-p max. (3) required tolerance on isolation resistors is 2%. instantaneous power dissipation (when transmitting) is approximately 0.5 w (typ), 0.8 w (max). (4) transformer pin numbering is correct for ddc bus-25679 or bus-29854 transformer. for the beta transformer (e.g., b-2203) or the qpl-21038-31 transformer (e.g., m21038/27-02), the winding sense and turns ratio are mechanically the same, but the pin numbering is reversed. therefore, it is necessary to reverse pins 8 and 4 or pins 7 and 5 in the diagram for the beta or qpl transformers. in the buffered mode, the output memena-out must be con- nected to the input memena-in . transparent mode the transparent mode (reference figure 20) supports an inter- face to up to 64k words of external shared ram and/or to a stanag-3910 component set. in the transparent mode, the memory control signals memena-out , memoe , and memwr are used to read and write data from/to external ram. memena- out is the bu-61559's chip select (cs ) output signal. for inter- nal ram accesses, the input memena-in should be asserted low. when there is no ongoing memory access, or for accesses to external ram, memena-in should be presented as a logic 1. in the transparent mode, the address buffers drive the cpu address onto the internal memory bus for cpu transfers; for 1553 transfers, the internal memory address is asserted on the external address bus. the data buffers are directed outward for bu-61559x1 bu-61559x2
19 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 figure 19. bu-61559 interconnection diagram for buffered mode the cpu reading internal ram (or registers), for 1553 write accesses, for 1553 read accesses from internal ram, and for internal transfers of received command words in rt mode. the data buffers are directed inward (toward the memory data bus) for cpu write accesses to internal ram (or registers) or for the 1553 reading external ram. it should be noted that a15 through a0 as well as d15 through d0 have internal pullup resistors to +5v. external pullup resistors are not required . figure 19 illustrates a generic interconnection of the bu-61559 in the buffered mode. in this configuration, only the 8k words of internal ram are used. no external address or data buffers are required. figure 20 illustrates a generic interconnection of the bu-61559 in the transparent mode. this configuration supports up to 64k words of address space. this may optionally include the 8k words of internal ram. in this configuration, external address and data buffers are required . bu-61559
20 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 figure 20. bu-61559 interconnection diagram for transparent mode bu-61559
21 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 address latch timing (buffered mode) figure 21 illustrates the operation and timing of the address input latches for the buffered interface mode. in the transparent mode, the address buffers, and select , mem/reg inputs are always transparent (msb/lsb not applicable). since the trans- parent mode requires the use of external buffers, external address latches would be required to demultiplex a multiplexed address bus. in the buffered mode however, the bu-61559's internal address may be used to perform the demultiplexing func- tion. figure 21. address latch timing the operation of the address latches is controlled by means of the addr_lat input. when addr_lat is high, the latch out- puts, which drive the bu-61559's internal memory and control bus, transparently track the state of the address inputs a15 through a00, and the input signals select , msb/lsb , and mem/reg . when addr_lat is low, the internal memory and control bus remain latched at the state of a15-a00, select , msb/lsb , and mem/reg just prior to the falling edge of addr_lat. notes for figure 21: 1. applicable to buffered mode only. address, select , and mem/reg latches are always transparent in the transparent mode of operation. 2. latches are transparent when addr_lat is high. internal values do not update when addr_lat is low. 3. msb/lsb input signal is applicable to 8-bit mode only (16/8 input = logic "0"). msb/lsb input is a "don't care" for 16-bit operation. t3 propagation delay from external input signals to internal signals valid t2 10 ns 10 ns 20 ns 10 ns min bu-61559 description ref address latch timing typ max unit addr_lat high delay to internal signals valid t1 20 ns addr_lat pulse width t4 input setup time prior to falling edge of addr_lat t5 input hold time following falling edge of addr_lat
22 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 processor interface timing figures 22 and 23 illustrate the timing for the host processor to access the bu-61559's internal ram in buffered mode. fig- ure 22 illustrates the buffered read cycle timing, while figure 23 shows the buffered mode write cycle. during a cpu transfer cycle, strbd and select must be sam- pled low for two consecutive clock cycles when the bu-61559 is not accessing the shared ram. at this time, the output signals ioen and memena-out are asserted low. ioen is used to enable external address and data tri-state buffers, if required. memena-in is the chip select (cs ) input to the bu-61559's internal ram. in the buffered mode, memena-out must be connected directly to memena-in . in the transparent mode, an external address decoder may be used to provide memena-in , as shown in figure 20. for a read cycle in the transparent mode, the output signal memoe is asserted low one-half clock cycle after ioen goes low. memoe will remain low until the end of the read transfer cycle. for a cpu write cycle in transparent mode, the output sig- nal memwr is asserted low for one clock cycle (62.5 ns nomi- nal), starting one clock cycle after ioen is asserted low. three clock cycles (nominally 187.5 ns) after ioen goes low, the bu-61559 will assert the handshake output read yd low. this informs the host processor that read data is available on d15-d0 or that write data has been stored. at this time, the cpu should bring select and strbd high, completing the transfer cycle. with two exceptions, the bu-61559 processor interface opera- tion for accessing registers and internal ram is essentially the same for both the buffered and transparent interface modes. one difference is the operation of the address latch/buffers, as described under the preceding sub-heading. a second difference is that for cpu accesses to external ram in the transparent mode, the data buffers remain in their high impedance state. hardware reset (mstclr ) the mstclr control input to the bu-61559 provides a hardware reset capability. a negative pulse of 50 ns or more will reset all internal logic of the aim-hy'er hybrid to its power turn-on or reset idle state. in most systems, mstclr is connected to the host processor's power turn-on reset circuit. bu-61559 interface to stanag 3910 high- speed protocol chip stanag 3910 high-speed protocol chip the 1553 bc/rt/mt is comprised of the ddc bu-61559 hybrid and the two bus-25679 transformers. in this interface, the bu- 61559 is configured in the transparent mode, interfacing to the host processor by means of external data and address buffers. this allows a stanag 3910 high speed protocol chip to moni- tor all 1553 words being transferred over the bu-61559's paral- lel data bus, d15-d00. the stanag 3910 remote terminal is comprised of a high- speed rt protocol chip, data retiming unit, a 20 mhz fiber optic transceiver, and ram for high-speed messages. in some imple- mentations, the data retiming unit and fiber optic transceiver may be one component. in general, the high speed protocol chip operates by monitor- ing the data bus, as well as various control signal outputs from the bu-61559. the bu-61559 control signals that may be moni- tored include bcstrcv , msg_err or , cmd_str , rxdt a_str , txdt a_str , and memena-out . the high speed protocol chip provides the memena-in input to the bu- 61559. in the transparent interface mode, command words and high- speed action words may be monitored on the bu-61559's exter- nal address and data buses. the high speed protocol chip per- forms all high-speed protocol operations, transmitting and receiving messages over the 3910 fiber optic bus by means of the data retiming unit and fiber optic transceiver. when the bu-61559 receives a transmit command to the high- speed subaddress, the high speed protocol chip captures the command word. the high speed protocol chip is then enabled by the bu-61559's memena-out and txdt a_str outputs to provide the high-speed status, bit, and last action words over the bu-61559's data bus. when it does this, the high speed protocol chip presents the memena-in input to the bu-61559 high, de-selecting the bu-61559's internal (or possibly external) ram. the bu-61559 then responds over the 1553 (3838) bus with the data words provided by the high speed protocol chip.
23 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 figure 22. cpu reading ram (shown for buffered mode) notes for figure 22: 1. for the 16-bit buffered nonzero wait configuration, transparent/b uffered must be connected to logic "0". zer o_w ait and dtreq /16/8 must be connected to logic "1". the inputs trig- ger_sel and msb/lsb may be connected to either +5v or ground. 2. select and strbd may be tied together. ioen goes low on the first rising clk edge when select strbd is sampled low (satisfying t1) and the bu-61559's protocol/memory management logic is not accessing the internal ram. when this occurs, ioen goes low, starting the transfer cycle. after ioen goes low, select may be released high. 3. mem/reg must be presented high for memory access, low for register access. 4. mem/reg and rd/wr are buffered transparently until the first falling edge of clk after ioen goes low. after this clk edge, mem/reg and rd/wr become latched internally. 5. the logic sense for rd/wr in the diagram assumes that polarity_sel is connected to logic "1". if polarity_sel is connected to logic "0", rd/wr must be asserted low to read. 6. the timing for ioen , read yd and d15-d0 assumes a 50 pf load. for loading above 50 pf, the validity of ioen , read yd , and d15-d0 is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max. 7. timing for a15-a0, mem/reg and select assumes addr-lat is connected to logic "1". refer to address latch timing for additional details. 8. internal ram is accessed by a11 through a0 (a13 through a0 for 61585, 61586, 61582 and 61583, a15 through a0 for 61688 and 61 689). registers are accessed by a4 through a0. 9. the address bus a15-a0 is internally buffered transparently until the first rising edge of clk after ioen goes low. after this clk edge, a15-a0 become latched internally. 10. setup time given for use in worst case timing calculations. none of the input signals are required to be synchronized to the system clock. when select and strbd do not meet the setup time of t1, but occur during the setup window of an internal flip-flop, an additional clock cycle will be inserted between the falli ng clock edge that latches mem/reg and rd/wr and the rising clock edge that latches the address (a15-a0). when this occurs, the pulse width of ioen falling to read yd falling (t11) increases by one clock cycle and the address hold time (t10) must be increased be one clock cycle. t3 mem/reg and rd/wr setup time following select and strbd low (notes 3,4,5,7) t2 107.5 2.8 ns ns 30 ns 35 ns 10 ns min bu-61559 description ref cpu reading ram or registers (shown for 16-bit, buffered, nonzero wait mode) typ max unit select and strbd low to ioen low (uncontended access) (notes 2,6) select and strbd low to ioen low (contended access) (notes 2,6) t1 20 ns select and strbd low setup time prior to clock rising edge (note 2,10) t4 address valid setup time following select and strbd low. t5 clock in rising edge delay to ioen falling edge (note 6) 0 ns 10 ns t6 select hold time following ioen falling (note 2) t7 mem/reg , rd/wr setup time prior to clock in falling edge (notes 3,4,5,7) 30 ns 30 ns t8 mem/reg , rd/wr hold time following clock in falling edge (notes 3,4,5,7) t9 address valid setup time prior to clock in rising edge (notes 7,8,9) 30 ns 170 170 187.5 187.5 205 205 ns ns t10 address hold time following clock in rising edge (notes 7,8,9,10) t11 ioen falling delay to read yd falling (reading ram) (notes 6,10) ioen falling delay to read yd falling (reading registers) (notes 6,10) 33 ns t12 output data valid prior to read yd falling (note 6) 35 ns ns t13 clock in rising edge delay to read yd falling (note 6) t14 read yd falling to strbd rising release time. 30 ns 0 ns t15 strbd rising edge delay to ioen rising edge and read yd rising edge (note 6) t16 output data hold time following strbd rising edge. 40 ns t17 strbd rising delay to output data tri-state 0 ns 60 ns t18 strbd high hold time from read yd rising t19 clock in rising edge delay to output data valid
24 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 figure 23. cpu writing ram (shown for buffered mode) notes for figure 23: 1. for the 16-bit buffered nonzero wait configuration transparent/b uffered must be connected to logic "0". zer o_w ait * and dtreq /16/8 must be connected to logic "1". the inputs trig- ger_sel and msb/lsb may be connected to either +5v or ground. 2. select and strbd may be tied together. ioen goes low on the first rising clk edge when select strbd is sampled low (satisfying t1) and the bu-61559's protocol/memory management logic is not accessing the internal ram. when this occurs, ioen goes low, starting the transfer cycle. after ioen goes low, select may be released high. 3. mem/reg must be presented high for memory access, low for register access. 4. mem/reg and rd/wr are buffered transparently until the first falling edge of clk after ioen goes low. after this clk edge, mem/reg and rd/wr become latched internally. 5. the logic sense for rd/wr in the diagram assumes that polarity_sel is connected to logic "1". if polarity_sel is connected to logic "0", rd/wr must be asserted high to write. 6. the timing for ioen and read yd outputs assumes a 50 pf load. for loading above 50 pf, the validity of ioen and read yd is delayed by an additional 0.14 ns/pf typ, 0.28 ns/pf max. 7. timing for a15-a0, mem/reg , and select assumes addr-lat is connected to logic "1". refer to address latch timing for additional details. 8. internal ram is accessed by a11 through a0 (a13 through a0 for 61585, 61586, 61582, and 61583 and a15 through a0 for 61688 an d 61689). registers are accessed by a4 through a0. 9. the address bus a15-a0 and data bus d15-d0 are internally buffered transparently until the first rising edge of clk after ioe n goes low. after this clk edge, a15-a0 and d15-d0 become latched internally. 10. setup time given for use in worst case timing calculations. none of the input signals are required to be synchronized to the system clock. when select and strbd do not meet the setup time of t1, but occur during the setup time of an internal flip-flop, an additional clock cycle will be inserted between the falling clock edge that latches mem/reg and rd/wr and the rising clock edge that latches the address (a15-a0) and data (d15-d0). when this occurs, the pulse width of ioen falling to read yd falling (t14) increases by one clock cycle and the address and data hold time (t12+t13) must be increased by one clock cycle. t3 mem/reg and rd/wr setup time following select and strbd low (notes 3,4,5,7) t2 107.5 2.8 ns ns 30 ns 50 ns 10 ns min bu-61559 description ref cpu writing ram or registers (shown for 16-bit, buffered, nonzero wait mode) typ max unit select and strbd low delay to ioen low (uncontended access) (notes 2,6) select and strbd low delay to ioen low (contended access) (notes 2,6) t1 10 ns select and strbd low setup time prior to clock rising edge (note 2,10) t4 address valid setup time following select and strbd low. t5 input data valid setup time following select and strbd low. 35 ns 10 ns t6 clock in rising edge delay to ioen falling edge (note 6) t7 select hold time following ioen falling (note 2) 30 ns 30 ns t8 mem/reg , rd/wr setup time prior to clock in falling edge (notes 3,4,5,7) t9 mem/reg , rd/wr hold time following clock in falling edge (notes 3,4,5,7) 30 ns 10 ns t10 address valid setup time prior to clock in rising edge (notes 7,8,9) t11 input data valid setup time prior to clock in rising edge 30 ns t12 address valid hold time following clock in rising edge (notes 7,8,9,10) 30 ns 170 187.5 205 ns t13 input data valid hold time following clock in rising edge (notes 9,10) t14 ioen falling delay to read yd falling (notes 6,10) 35 ns ns t15 clock in rising edge delay to read yd falling (note 6) t16 read yd falling to strbd rising release time. 30 ns t17 strbd rising edge delay to ioen rising edge and read yd rising edge (note 6) 0 ns t18 strbd valid high hold time from read yd rising edge
25 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 logic +5v supply +5v logic 14 27 logic ground logic gnd 21 78 ch. a -15v/-12v supply -15/-12va 39 42 ch. a +5v supply +5va 77 43 ch. a transceiver ground gnda 38 44 ch. b -15v/-12v supply -15/-12vb 18 35 ch. b +5v supply +5vb 58 36 ch. b transceiver ground gndb 19 37 signal name pin no. pin no. pin no. description dip flat power and ground (8) 16-bit bidirectional data bus. this bus is used for interfacing the host processor to the internal registers and 8k words of ram. in addition, in the transparent mode, this bus allows data transfers to take place between the internal proto- col/memory management logic and up to 64k x 16 of external ram. most of the time, the outputs for d15 through d0 are in their high impedance state. they drive outward when the host cpu reads the internal ram or registers, or when the protocol /memory management logic is accessing (either reading or writing) internal ram or writing to external ram when in the transparent mode. d15-d0 assume their high-impedance states fol- lowing power turn-on reset. d15 (msb) 48 16 d14 8 15 d13 47 14 d12 7 13 d11 46 12 d10 6 11 d9 45 10 d8 5 9 d7 44 8 d6 4 7 d5 43 6 d4 3 5 d3 42 4 d2 2 3 d1 41 2 d0 (lsb) 1 1 signal name description dip flat data bus (16) 16-bit bidirectional address bus. in both the buffered and transparent modes, the host cpu accesses the bu-61559 reg- isters and 8k words of internal ram by means of a12 through a0. in the trans- parent mode, a15-a0 drive outward (towards the cpu) in order for the 1553 protocol/memory management logic to access up to 64k x 16 of external ram. most of the time, including immediately after power turn-on reset, the a15-a0 outputs will be in their disabled (high impedance) state. a15 (msb) 29 62 a14 67 63 a13 28 64 a12 66 65 a11 27 66 a10 65 67 a9 26 68 a8 64 69 a7 25 70 a6 63 71 a5 24 72 a4 62 73 a3 23 74 a2 61 75 a1 22 76 a0 (lsb) 60 77 signal name description dip flat address bus (16) table 7. signal descriptions by functional groups
26 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 used to select between the transpar- ent (when strapped to logic 1) and buffered (when strapped to logic 0) modes for the host processor inter- face. transparent/ b uffered 35 50 strobe data. used in conjunction with select to initiate and control the data transfer cycle between the host processor and the bu-61559. strbd (i) 34 52 generally connected to a cpu address decoder output to select the bu-61559 for a transfer to/from either ram or register. may be tied to strbd . select (i) 74 49 memory/register. generally connected to either a cpu address line or address decoder output. selects between mem- ory access (mem/reg = 1) or register access (mem/reg = 0). mem/reg (i) 33 54 read/write. for a host processor access, selects between reading (rd/wr = 1) and writing (rd/wr = 0). rd/wr (i) 36 48 tri-state control for external address and data buffers. generally not need- ed in the buffered mode. when low, external buffers should be enabled to allow the host processor access to the bus-61669's ram and registers. ioen (o) 73 51 handshake output to host processor. for a read access, signals that data is available to be read on d15 through d0. for a write cycle, signals that data has been transferred to a register or ram location. read yd (o) 75 47 interrupt request output. if the level/pulse interrupt bit (bit 3) of configuration register #2 is low, a negative pulse of approximately 500 ns in width is output on int . if bit 3 is high, a low level interrupt request out- put will be asserted on int . int (o) 72 53 signal name pin no. description dip flat processor interface (8) asserted low during both host proces- sor and 1553 protocol/memory man- agement memory transfer cycles. used as a memory chip select (cs ) signal for external ram in the transparent mode. memena-out (o) 31 58 chip select (cs ) input to 8k x 16 of internal shared ram. if only internal ram is used (always the case in the buffered mode), connect directly to memena-out . memena-in (i) 69 59 memory output enable/address latch. in transparent mode, output used to enable data outputs for external ram read cycles. in buffered mode, input used to configure the internal address buffers in latched mode (when low) or transparent mode (when high). memoe (o)/ addr_lat (i), 30 60 memory write. asserted low during memory write transfers to strobe data into internal or external ram. used in transparent mode. memwr (o) 68 61 signal name pin no. description dip flat memory interface and address latch control (4) analog transmit/receive input/outputs. connect directly to 1553 isolation trans- formers. tx/rx-a (i/o) 40 40 tx/rx-a (i/o) 78 41 tx/rx-b (i/o) 20 39 tx/rx-b (i/o) 59 38 signal name pin no. description dip flat 1553 isolation transformer interface (4) remote terminal address inputs remote terminal address parity. must provide odd parity sum with rtad4- rtad0 in order for the rt to respond to non-broadcast commands. rtad4 (msb) (i) 11 21 rtad3 (i) 49 18 rtad2 (i) 50 20 rtad1 (i) 9 17 rtad0 (msb) (i) 10 19 rtad (i) 51 22 signal name pin no. description dip flat rt address (6) table 7. signal descriptions by functional groups (cont)
27 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 16 mhz clock input. clock in (i) 32 56 master clear. negative true reset input, normally asserted low following power turn-on. mstclr (i) 71 55 in command. in bc mode, asserted low throughout processing cycle for each message. in rt mode, asserted low following receipt of command word and kept low until completion of current message sequence. in monitor mode, goes low following monitor start command, kept low while monitor is on- line, goes high following reset com- mand. incmd (o) 70 57 the 1553 channel a and/or channel b transmitters may be inhibited by assert- ing the respective tx_inh input(s) high. * tx_inh_a (i) 76 45 tx_inh_b (i) 57 34 if this input is asserted low the subsystem flag bit will be set in the bu-61559's rt status word. a low on the ssfla g input overrides a logic ?1? of the respective bit (bit 8) of configuration register #1. ssfla g (i) 37 46 in bc or rt modes, this output will be asserted as a low level following a word or format error and remain low until the start of the next message. msg_err (o) 12 23 in rt/transparent mode, this output will pulse low for nominally 62.5 ns (signal is one clock cycle wide) and occurs in the middle of the transfer cycle, coinci- dent with the memwr pulse for writing the command word to ram. cmd_str (o) 13 25 in rt/transparent mode, this output will pulse low for nominally 62.5 ns (signal is one clock cycle wide) and occurs during the third of four clock cycles dur- ing a data word write cycle, in the same time frame that memwr writes the received data word to ram. rx_dt a_str (o) 52 24 in rt/transparent mode, this output will pulse low for nominally 62.5 nsec (sig- nal is one clock cycle wide) and occurs during the third of four clock cycles dur- ing a data word read cycle. t x_dt a_str (o) 53 26 signal name pin no. description dip flat miscellaneous (16) broadcast enable. if connected to logic 1, the bu-61559 will recognize rt address 31 as the broadcast address. if connected to logic 0, rt address 31 may be used as a discrete rt address. bro_ena (i) 54 28 broadcast command received is an active low signal that occurs 1.35 to 2.25 s following the mid-parity bit crossing of a received broadcast com- mand word that remains low until receipt of a subsequent command word to the bu-61559?s own rt address. bcstrcv (o) 16 31 illegalization enable. if connected to logic 1, designates shared ram addresses 0300-03ff to be dedicated for command illegalization in rt mode. if set to logic 0, illegalization is disabled and addresses 0300-03ff may be used for stack or message data. has no effect in bc or mt modes. illena (i) 17 33 external time tag clock input. for bc/rt modes. use may be designated by means of configuration register # 2. if not used, should be connected to +5v or ground. tag_clk (i) 15 29 in rt mode, is updated following every valid, nonbroadcast message. will be asserted low if the rt fails its loopback test (invalid or mismatch to last trans- mitted word) or if a 768 s timeout con- dition occurs. cleared by reset or as a result of next valid, non-broadcast mes- sage. r t_f ail (o) 55 30 active low input used to control rt flag bit in rt status word. if r tf ail is low, the rt flag bit will be set. may be connected to r tf ail . r tfla g (i) 56 32 signal name pin no. description dip flat miscellaneous (16) (cont) * the operation of the tx_inh_a/b inputs also effects the operation of the bc off- line self test. if the inhibit is high when an off-line bc self test is run, a ?loop test? failure will occur. table 7. signal descriptions by functional groups (cont)
28 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 1.800 max (46) 1.500 (38) 1.800 (46) index denotes pin 1 2.100 max (53) 1.900 (48) 0.210 max (5.33) 0.100 typ (2.54) 0.250 0.010 (6.35 0.25) pin numbers for reference only 1.650 (42) 0.018 0.002 dia typ (0.46 0.05) 59 20 40 78 60 21 41 1 2 see detail "a" 0.050 typ (1.27) detail "a" note: dimensions are in inches (mm). figure 24. bu-61559d mechanical outline (78-pin ceramic ddip) 38 eq. sp. @ 0.050 = 1.90 tol noncum (1.27 = 48.26) 0.400 min typ (10.16) 0.050 typ (1.27) 0.100 0.010 typ (2.54 0.25) 0.210 max (5.33) 39 40 1 78 1.800 max (45.72) notes: lead cluster to be centralized about case center line within 0.010. 2. dimensions are in inches (mm). 0.018 0.002 typ (0.46 0.05) see detail "a" detail "a" 1 pn 1 denoted by index tab on lead braze 2.100 max (53.34) 0.010 0.002 typ (0.25 0.05) pin numbers for reference only 1.824 max (46.32) 0.010 (0.254) 0.050 (1.27) typ 1 figure 25. bu-61559f mechanical outline (78-pin ceramic flat pack)
29 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 ordering information bu-61559xx-xxxx supplemental process requirements: s = pre-cap source inspection l = pull test q = pull test and pre-cap inspection k = one lot date code w = one lot date code and precap source y = one lot date code and 100% pull test z = one lot date code, precap source and 100% pull test blank = none of the above test criteria: 0 = standard testing process requirements: 0 = standard ddc practices, no burn-in 1 = mil-prf-38534 compliant 2 = b* 3 = mil-prf-38534 compliant with pind testing 4 = mil-prf-38534 compliant with solder dip 5 = mil-prf-38534 compliant with pind testing and solder dip 6 = b* with pind testing 7 = b* with solder dip 8 = b* with pind testing and solder dip 9 = standard ddc processing with solder dip, no burn-in temperature range/data requirements: 1 = -55c to +125c 2 = -40c to +85c 3 = 0c to +70c 4 = -55c to +125c with variables test data 5 = -40c to +85c with variables test data 6 = custom part (reserved) 7 = custom part (reserved) 8 = 0c to +70c with variables test data voltage requirements: 1 = +5 volts and -15 volts 2 = +5 volts and -12 volts package: d = 78-pin ceramic qip f = 78-pin ceramic flat pack product type: bu-61559 = aim hy?er notes: 1. standard ddc processing with burn-in and full temperature test. see table on following page. 2. the above products contain tin-lead solder finish as applicable to solder dip requirements.
notes: 30 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 table 1 1015 (note 1) , 1030 (note 2) burn-in notes: 1. for process requirement "b*" (refer to ordering information), devices may be non-compliant with mil- std-883, test method 1015, paragraph 3.2. contact factory for details. 2. when applicable. 3000g 2001 constant acceleration c 1010 temperature cycle a and c 1014 seal 2009, 2010, 2017, and 2032 inspection condition(s) method(s) mil-std-883 test standard ddc processing for hybrid and monolithic hermetic products
31 data device corporation www.ddc-web.com bu-61559 series e-03/06-0 notes:
32 e-03/06-0 printed in the u.s.a. the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. please visit our web site at www.ddc-web.com for the latest information. 105 wilbur place, bohemia, new york, u.s.a. 11716-2482 for technical support - 1-800-ddc-5757 ext. 7771 headquarters, n.y., u.s.a. - tel: (631) 567-5600, fax: (631) 567-7358 southeast, u.s.a. - tel: (703) 450-7900, fax: (703) 450-6610 west coast, u.s.a. - tel: (714) 895-9777, fax: (714) 895-4988 united kingdom - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 ireland - tel: +353-21-341065, fax: +353-21-341568 france - tel: +33-(0)1-41-16-3424, fax: +33-(0)1-41-16-3425 germany - tel: +49-(0)89-150012 -11, fax: +49-(0)89-150012 -22 japan - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com data device corporation registered to iso 9001:2000 file no. a5976 r e g i s t e r e d f i r m ? u

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